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 STS15N4LLF3
N-channel 40V - 0.0042 - 15A - SO-8 STripFETTM Power MOSFET
General features
Type STS15N4LLF3

VDSS 40V
RDS(on) <0.005
ID 15A
Optimal RDS(on)x Qg trade-off @ 4.5V Conduction losses reduced Switching losses reduced
SO-8
Description
This N-channel enhancement mode Power MOSFET is the latest refinement of STMicroelectronic unique "Single Feature SizeTM" strip-based process with less critical aligment steps and therefore a remarkable manufacturing reproducibility. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and low gate charge.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STS15N4LLF3 Marking 15N4LLPackage SO-8 Packaging Tape & reel
November 2006
Rev 2
1/12
www.st.com 12
Contents
STS15N4LLF3
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................. 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STS15N4LLF3
Electrical ratings
1
Table 1.
Symbol VDS VGS VGS ID ID IDM
(2) (1)
Electrical ratings
Absolute maximim ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Single pulse avalanche energy Value 40 16 18 15 9.3 60 2.7 2 Unit V V V A A A W J
PTOT EAS
(3)
1. Guaranteed for test time < 15ms 2. Pulse width limited by Tjmax 3. Starting Tj =25C, ID =7.5A, VDD =25V
Table 2.
Symbol
Thermal resistance
Parameter Value 47 -55 to 150 -55 to 150 Unit C/W C C
Rthj-pcb(1) Thermal resistance junction-pcb max Tl Tstg Maximum lead temperature for soldering Storage temperature
1. When mounted of FR-4 board with 1 inch2 pad, 2oz of Cu and t< 10sec
3/12
Electrical characteristics
STS15N4LLF3
2
Electrical characteristics
(TJ = 25 C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage Current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS= 0 VDS = max rating, VDS =max rating @125C VGS = 16V VDS= VGS, ID = 250A VGS= 10V, ID= 7.5A VGS= 4.5V, ID= 7.5A 1 0.0042 0.005 0.005 0.007 Min. 40 10 100
200
Typ.
Max.
Unit V A A nA V
Table 4.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions Min. Typ. 2530 574 29 21.5 6.9 8.2 1 3 28 Max. Unit pF pF pF nC nC nC
VDS = 25V, f=1 MHz, VGS= 0 VDD = 20V, ID = 15A VGS = 4.5V (see Figure 13) f=1 MHz Gate DC Bias = 0 Test signal level = 20mV open drain
5
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 20V, ID = 7.5A, RG = 4.7, VGS = 10V (see Figure 15) VDD = 20V, ID = 7.5A, RG = 4.7, VGS = 10V (see Figure 15) Min. Typ. 17 25 62 9 Max. Unit ns ns ns ns
4/12
STS15N4LLF3
Electrical characteristics
Table 6.
Symbol ISD ISDM(1) VSD (2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 15A, VGS = 0 ISD = 15A, VDD = 30V, di/dt = 100A/s, Tj = 150C (see Figure 14) 43 64 3 Test conditions Min. Typ. Max. 15 60 1.2 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300s, duty cycle 1.5%
5/12
Electrical characteristics
STS15N4LLF3
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Normalized BVDSS vs temperature
Figure 6.
Static drain-source on resistance
6/12
STS15N4LLF3 Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
7/12
Test circuit
STS15N4LLF3
3
Test circuit
Figure 13. Gate charge test circuit
Figure 12. Switching times test circuit for resistive load
Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit
Figure 16. Unclamped inductive waveform
Figure 17. Switching time waveform
8/12
STS15N4LLF3
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: twww.st.com
9/12
Package mechanical data
STS15N4LLF3
SO-8 MECHANICAL DATA
DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
10/12
STS15N4LLF3
Revision history
5
Table 7.
Date
Revision history
Revision history
Revision 1 2 First release Corrected part number Changes
09-Jun-2006 22-Nov-2006
11/12
STS15N4LLF3
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